1 ps8878j 05/02/07 enable1 bclk[0:4] bclk5 5 sync sync enable2 xtal_in xtal_out block diagram pi6cl10806 1.2v/1.5v, 250mhz, low skew 1:6 crystal to lvcmos clock buffer description pericom semiconductor?s pi6cl10806 is a low skew six output crystal oscillator drivers. crystal oscillator input range is from 10mhz to 40mhz. if xtal_in is driven with a signal source, then the input frequency can be as high as 200mhz. pi6cl10806, the outputs are con gured into 2 groups: a ve output and a single output; each with independent output enable. pi6cl10806 has a wide range of operating voltages: 1.2v and 1.5v. this feature paired with the low output-to-output and part-to-part skew makes the device ideal for low voltage, low power, high frequency single ended applications; such as networking features ? six low skew outputs: < 80ps ? crystal oscillator input: 10mhz to 40mhz ? switching frequency up to 250 mhz ? fast output rise/fall time: < 800ps ? synchronous output enables ? industrial temperature range: ?40c to +85c ? 1.2v and 1.5v operation ? packaging (pb-free & green available): ? 16-pin 173-mil wide tssop (l) pin description pin name description enable1, enable2 active high output enable inputs xtal_in crystal interface xtal_out crystal interface bclk[0:5] clock outputs gnd ground v dd core power v ddo output power truth table (1) inputs outputs enable1 enable2 bclk[0:4] bclk5 llll l h l switching h l switching l h h switching switching note: 1. h = high voltage level, l = low voltage level xtal_in xtal_out 1 16 enable1 enable2 2 15 bclk5 gnd 3 14 bclk4 bclk0 4 13 v ddo v ddo 512 gnd bclk1 6 11 bclk3 gnd 7 10 v dd bclk2 8 9 pin con g u ra tion 07-0116
2 ps8878j 05/02/07 pi6cl10806 1.2v/1.5v low skew 1:6 crystal to lvcmos clock buffer storage temperature ...........................................................?65c to +150c v dd, v ddo voltage ...............................................................?0.5v to +3.6v output voltage (max. 3.6v) .......................................... ?0.5v to v dd +0.5v input voltage (max 3.6v) .............................................. ?0.5v to v dd +0.5v 1.5v absolute maximum ratings (above which the useful life may be impaired. for user guidelines only, not tested.) note: stresses greater than those listed under maximum rat ings may cause permanent damage to the device. this is a stress rating only and functional op er a tion of the device at these or any other con di tions above those indicated in the operational sec tions of this spec i ca tion is not implied. ex po sure to absolute maximum rating con di - tions for extended periods may affect re li abil i ty. 1.5v i/o dc characteristics (over operating range: v dd = 1.5v 0.1v, t a = -40 to 85c) parameters description test conditions (1) min. typ. (2) max. units v ddo i/o supply voltage 1.4 1.5 1.6 v ih input high voltage logic high level 0.65 x v dd v dd v v il input low voltage logic low level -0.3 0.33 x v dd v oh output high voltage v ddo = min., v in = v ih or v il i oh = -1ma 1.05 v i oh = -8ma 0.75 v ol output low voltage v ddo = min., v in = v ih or v il i ol = 1ma 0.35 i ol = 8ma 0.65 notes: 1. for max. or min. conditions, use appropriate operating range values. 2. typical values are at v cc = 2.5v, +25c ambient and maximum loading. 1.5v i/o ac characteristics (over operating range: v dd /v ddo = 1.5v 0.1v, t a = -40 to 85c) parameters de scrip tion test conditions (1) min. typ max. units f out output frequency using crystal 10 40 mhz external clock (2) 0 ` 200 t dc output duty cycle @ v ddo /2 47 53 % t r /t f clkn rise/fall time 20% to 80% 150 3500 ps t sk(o) (3) output to output skew between any two outputs of the same device @ same transition @v ddo /2 80 ps t dis, t en ( 4) output enable/disable @v ddo /2 4 cycles notes: 1. unless noted otherwise, all parameters are tested with xtal @ f <= fxtal_max,; outputs are terminated @ 50 to v ddo /2 , see waveforms. 2. external clock source is driving xtal_in input 3. identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 4. these parameters are guaranteed, but not tested. min & max delay is 4 cycles. 07-0116
3 ps8878j 05/02/07 pi6cl10806 1.2v/1.5v low skew 1:6 crystal to lvcmos clock buffer 1.2v i/o dc characteristics (over operating range: v dd = 1.2v 0.1v, t a = -40 to 85c) parameters description test conditions (1) min. typ. (2) max. units v ddo i/o supply voltage 1.1 1.2 1.3 v v ih input high voltage logic high level 0.65*v dd v dd v il input low voltage logic low level -0.3 0.35*v dd v oh output high voltage v dd = min., v in = v ih or v il i oh = -2ma 0.85 i oh = -8ma 0.55 v ol output low voltage v dd = min., v in = v ih or v il i ol = 2ma 0.35 i ol = 8ma 0.35 notes: 1. for max. or min. conditions, use appropriate operating vdd and ta values. 2. typical values are at v cc = 1.8v, +25c ambient and maximum loading. storage temperature ...........................................................?65c to +150c v ddo ,v dd voltage ................................................................?0.5v to +2.5v output voltage (max 2.5v) .......................................... ?0.5v to v dd +0.5v input voltage (max 2.5v) ............................................. ?0.5v to v dd +0.5v 1.2v absolute maximum ratings (above which the useful life may be impaired. for user guidelines only, not tested.) note: stresses greater than those listed under maximum rat ings may cause permanent damage to the device. this is a stress rating only and functional op er a tion of the device at these or any other con di tions above those indicated in the operational sec tions of this spec i ca tion is not implied. ex po sure to absolute maximum rating con di - tions for extended periods may affect re li abil i ty. 1.2v i/o ac characteristics (over operating range: v dd/ v ddo = 1.2v 0.1v, t a = -40 to 85c) parameters de scrip tion test conditions (1) min. typ max. units f out output frequency using crystal 10 40 mhz external clock (2) 0 200 t dc output duty cycle @ v ddo /2 47 53 % t r /t f clkn rise/fall time 20% to 80% 150 350 ps t sk(o) (3) output to output skew between any two outputs of the same device @ same transition @v ddo /2 80 ps t dis, t en ( 4) output enable/disable @v ddo\ /2 4 cycles notes: 1. unless noted otherwise, all parameters are tested with xtal @ f <= fxtal_max,; outputs are terminated @ 50 to v ddo /2 , see waveforms. 2. external clock source is driving xtal_in input 3. identical conditions: loading, transitions, supply voltage, temperature, package type and speed grade. 4. these parameters are guaranteed, but not tested. min & max delay is 4 cycles. 07-0116
4 ps8878j 05/02/07 pi6cl10806 1.2v/1.5v low skew 1:6 crystal to lvcmos clock buffer waveforms bclk5 bclk[0:4] enable2 enable1 output to output skew ? t sk (o) bclkx v oh v ddo /2 v ol t sk(o) bclky v oh v ddo /2 v ol t sk(o) t pzl v ddo /2 0v t pw v ddo t period t dc = (t pw / t period ) x 100% duty cycle ? t dc enable1, enable2 timing diagram v dd v ddo gnd [v ddo /2] zC50 scope 50 ac test circuit load phase noise and jitter (over operating range: v dd = v ddo = 1.2v 0.1v, and v dd = v ddo = 1.5v 0.1v, t a = -40 to 85c) symbol de scrip tion test conditions (1) min. typ max. units t jit random rms phase jitter 25mhz @ integration range 1mhz ~ 20mhz 2.5 ps pn 1 phase noise power offset range 10hz -60 dbc/hz pn 2 phase noise power offset range 100hz -90 dbc/hz pn 3 phase noise power offset range 1khz -120 dbc/hz pn 4 phase noise power offset range 10khz -150 dbc/hz note: v dd /v ddo = 1.2v 0.1v, 1.5v 0.1v 07-0116
5 ps8878j 05/02/07 pi6cl10806 1.2v/1.5v low skew 1:6 crystal to lvcmos clock buffer crystal characteristic (link to "http://www.pericom.com/saronix" for more detailed crystal speci cations) parameters de scrip tion min typ max. units osc mode mode of oscillation fundamental freq frequency 10 25 40 mhz esr (1) equivalent series resistance 30 200 ohm c load load capacitance 16 32 pf c shunt shunt capacitance 7 pf drive operating drive level 0.5 mw correlation drive level 0.1 mw note: 1. esr value is dependent upon frequency of oscillation application notes crystal circuit connection the following diagram shows pi6cl10806 crystal circuit connection with a parallel resonant crystal. for the c l =18pf crystal, it is suggested to use c1=15pf, c2=20pf. c1 and c2 can be adjusted to ne tune to the tar- get ppm of crystal oscillation according to different board layouts. r1=100 is strongly suggested. crystal oscillator circuit c1 15pf crystal (c l = 18pf) c2 20pf 100 7 r1 xtal_in xtal_out 07-0116
6 ps8878j 05/02/07 pi6cl10806 1.2v/1.5v low skew 1:6 crystal to lvcmos clock buffer pi6c10806 ordering information (1,2,3) ordering code package code package description pi6cl10806 l pb-free and green 16-pin 173-mil tssop notes: 1. thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb-free and green 3. x suf x = tape/reel package mechanical - 16-lead tssop (l) .193 .201 .047 max. .002 .006 seating plane .0256 bsc .018 .030 .004 .008 .252 bsc 1 16 .169 .177 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 1.20 4.9 5.1 0.65 0.19 0.30 .007 .012 07-0116
7 ps8878j 05/02/07 pi6cl10806 1.2v/1.5v low skew 1:6 crystal to lvcmos clock buffer pericom/saronix miniature low pro le smd quartz crystal ordering information type / package 49smlb = 2 contact, 4mm high 49sab = 4 contact, 5 mm high 49snc = 4 contact, 5mm high 49sub = 6 contact, 5mm high frequency frequency (in mhz) = 0x.xxxx, xx.xxxx (a zero is used in front of frequencies under 10 mhz) b = bt-cut, 26.8 to 50 mhz ? (dash) = at-cut parallel resonance blank = at-cut series resonance options (t) = tape and reel (full increments only) 1000 pieces blank = bulk calibration / stability / temp range ggc = 30ppm / 30ppm / -20 to +70c ghe = 30ppm / 50ppm / -40 to +85c hje = 50ppm / 100ppm / -40 to +85c *others available load capacitance xx = parallel resonance (specify load) blank = series resonance examples: 25.0000mhz, 30ppm calib, 30ppm stability, -20 to +70c (commercial), 16pf 49smlb25.0000-16ggc 49smlb25.0000-16ggc?e (for lead-free) 25.0000mhz, 30ppm calib, 30ppm stability, -40 to +85c (industrial), 16pf 49smlb25.0000-16ghe 49smlb25.0000-16ghe?e (for lead-free) 49xxx xxx ? xx xxx x (x) pad connection con gurations ?e (dash e) = lead (pb)-free rohs compliant version blank = standard version packaging information: hc-49 package marking information line 1: s = saronix xxx = calib/stability/temp code yywwx = date code line 2: frequency (up to 7 digits, including decimal point) bt-cut = b or at-cut parallel = ?(dash) or at-cut series = leave blank xx = load capacitance (leave blank if series) sxxxyywwx 25.0000-xx land pattern land pattern pericom semiconductor corporation ? 1-800-435-2336 ? www.pericom.com 07-0116
|
